Here’s the situation: our processors typically have somewhere between 4-30 general purpose registers. In a load/store architecture like ARM, computation can only be done on registers, and 4-30 pieces of data is simply not enough. Why not, then, make a computer with millions of registers? There are several reasons:
The fix is to create another level of storage. We call it main memory, and it is often built out of dynamic RAM (DRAM). We’ll discuss how SRAM and DRAM are implemented. SRAM uses a couple of NOT gates feeding back into each other and a couple of transistors for activating lines out of these NOT gates. That’s 6 transistors in total. Because the NOT gates are in a cycle, they will hold onto the bit value as long as the machine is powered on. DRAM is implemented using a transistor to activate the line and a capacitor to hold the bit. That’s less hardware, making DRAM cheaper. A disadvantage of DRAM is that capacitors leak and need periodic recharging. Another disadvantage is that reading from a capacitor is slower; the capacitor is not a “high-pressure” voltage source, and it takes some time for it to propagate.
In general, we want our data storage to be like our cars: fast, cheap, and roomy. But these dreams are at odds with each other. To overcome these competing needs, we can make a stack of all these technologies: registers, cache, main memory, disk, the cloud, and so on. This stack is called the memory hierarchy.
We will examine each level of the hierarchy and consider its latency, its capacity, and cost per megabyte. Some of these numbers will be in orders of magnitude that our brains simply can’t fathom, so we’ll try to convert them to more accessible measures.
See you next class!